In the development process of Graphics Processing Unit (GPU) system, memory commissioning and qualification test is a key step for guaranteeing that memory design can meet the expected performance (i.e. running at Power-On Reset (POR) clock). During commissioning Synchronous Dynamic Random Access Memory (SDRAM), it is quite often to meet memory faults caused by transaction error on address bus. The reason is that there are too many loads on the address bus, so its signal integrity has been degraded. For example, as shown in FIG. 1, a CMD signal from GPU which includes an address signal may have up to 8 loads. The T branches introduce stubs and additional vias in Printed circuit board (PCB) layout which makes the signal integrity worse.
When the memory faults are investigated, it is more difficult to find out which address bit has error than to find out which data bit has error. In general, it is needed to test every address bit in the lab, and then to compare eye diagrams of all address bits to figure out the fault address bit(s). But due to no clear criterion to judge whether an eye diagram is good or bad, so it is difficult to confirm whether the suspected address bit is a fault address bit with a signal integrity problem. Currently the adopted confirmation way is to improve the layout of the suspected address bit and build a new hunch of PCB for verifying. Thus, this commissioning process is quite time consuming and not cost-efficient.